The invention relates to a diffused metal oxide semiconductor transistor (DMOST) structure and specifically relates to a means for increasing the drain breakdown voltage in devices that are limited by avalanche breakdown. This is the limiting voltage breakdown mechanism where the device dimensions are made large enough to preclude punch through or reach through of the electric field depletion region. Avalance breakdown occurs when the semiconductor internal electric field gradient exceeds a value that results in spontaneous carrier generation. Once this action starts the thus-created carriers are accelerated in the electric field and, by collisions with the semiconductor crystal lattice, generate additional carriers. When the carrier generation ratio becomes greater than unity the process is regenerative and will rapidly proceed towards infinity. This form of breakdown interrupts normal device operation and results in a critical voltage limitation for the device.
FIG. 1 shows a typical cross section of a vertical DMOST employed in the semiconductor industry. The vertical dimensions of the drawing have been exaggerated with respect to the horizontal dimensions for clarity. The device employs conventional planar construction. The semiconductor drain layer 10 can be a well known epitaxial semiconductor layer of N type conductivity located upon an N+ substrate 11. This N+ substrate can be a heavily doped semiconductor wafer where the DMOST is to be produced as a discrete element. Alternatively, layer 11 can be a buried conductive layer of heavily doped material as is well known in the monolithic semiconductor integrated circuit art. At the surface of the semiconductor layer 10 a planar junction region 12 is created by diffusing a P type impurity therein. While a cross-section is shown in FIG. 1, P region 12 is actually in the form of a ring that can have any desired surface configuration. It can be a simple circle or, as is more commonly employed, it can be hexagonal in shape so that a plurality of such elements can be nested together on a semiconductor wafer surface. The plurality of such elements are connected in parallel by planar device metallization so that they act together as a single element. While each of the elements conduct only a relatively small current, enough such elements can be employed in parallel to provide a desired current value. In practice, several thousand such elements can be connected together to provide many amperes of current.
Inside region 12 a second N+ conductivity source region 13 is diffused into the semiconductor surface as shown. Region 13 extends part way through region 12 and its inner edge is spaced from the inner edge of region 12 so that a controlled spacing is achieved. Dashed lines 14 span this spacing and serve to define the DMOST channel region. Gate metallization 16 spans the channel region and actually extends slightly over the periphery of region 13. The gate metallization is shown suspended over the surface of the semiconductor, but is in fact, located on top of a thin gate oxide. The planar oxide, as well as the conventional planar metallization, is not shown in FIG. 1. Their omission is for the purpose of improving the clarity of the drawings and it is to be understood that such planar artifacts are indeed present. The thickness of the oxide layer under gate metallization is controlled in the fashion of conventional MOST practice to control the DMOST threshold voltage V.sub.T.
If a positive potential is applied to metal 15 it will act to repel the majority P type carriers and attract N type minority carriers in region 12 just under the thin oxide. This action, at some voltage level determined by the oxide thickness and the doping level in the channel region, will drive the P type region into its inverted state thus creating a channel region that is defined by dashed lines 14.
The device electrodes are shown schematically. The source contact is made to region 13 and a parallel connection to region 12 forms the DMOST body connection. Thus, terminal 20 is the SOURCE/BODY electrode, terminal 19 is the GATE electrode and terminal 18, which is made to region 11, is the DRAIN electrode. Thus, the DMOST has its body 12 (or backgate) shorted to its source 13 as shown in the associated schematic diagram.
In a typical DMOST construction layer 11 is a heavily doped semiconductor wafer and the drain contact 18 is made to the opposite wafer face as shown. Alternatively, layer 11 is a conductive buried layer about a micron thick located upon a P type semiconductor substrate wafer in accordance with monolithic integrated circuit practice. N type layer 10 is typically made about 14 microns thick and region 12 extends about 2.5 microns into the surface. Region 13 extends for about a micron into region 12. P type body region 12 typically has a surface carrier concentration of about 3.5.times.10.sup.17 /cm.sup.3. Region 10 has a uniform carrier concentration of about 5.times.10.sup.15 /cm.sup.3. Region 11 has a carrier concentration of about 5.times.10.sup.18 /cm.sup.3, which provides a low resistance ohmic area contact to drain region 10. For the above-mentioned conditions, the drain reach-through voltage from region 12 is greater than 120 volts. However, for the carrier concentration in region 10, the avalanche voltage will be lower than the reachthrough.
In a well known alternative embodiment of the vertical DMOST, the semiconductor surface lying inside the inner periphery of region 12 can be made to have a reduced conductivity.
Further, with respect to the prior art, FIG. 2 is a simplified cross-section of the junction portion of FIG. 1, as defined by dashed line 2. In FIG. 2, dashed line 3 extends vertically through the junction structure and FIG. 3 is a graph that plots typical carrier concentration along this line. It can be seen that the junction is located about 2.5 microns below the surface. To the left of the junction P type material in region 12 is present and to the right the N type material of region 10 exists. It will be noted that the doping in region 10 is uniform as a result of epitaxial deposition while body region 12, which is a planar diffusion, is exponential.
Dashed line 4 of FIG. 2 is angled at about 22 degrees with respect to the surface and represents an expanded plot of carrier concentration as shown in the graph of FIG. 4. This graph extends for over 12 microns and shows the PN junction location at 6 microns. The purpose of the angle is to expand the profile and FIG. 4 represents an actual device plot using an angle-lapped specimen.